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IS42S86400B IS42S16320B, IS45S16320B 64M x 8, 32M x 16 512Mb SYNCHRONOUS DRAM FEATURES * Clockfrequency:166,143,133MHz * Fullysynchronous;allsignalsreferencedtoa positive clock edge * Internalbankforhidingrowaccess/precharge * Powersupply Vdd Vddq IS42/45S16320B 3.3V 3.3V IS42S86400B * LVTTLinterface * Programmableburstlength -(1,2,4,8,fullpage) * Programmableburstsequence: Sequential/Interleave * AutoRefresh(CBR) * SelfRefresh * 8Krefreshcyclesevery64ms * Randomcolumnaddresseveryclockcycle * ProgrammableCASlatency(2,3clocks) * Burstread/writeandburstread/singlewrite operations capability * Burstterminationbyburststopandprecharge command * Availablein54-pinTSOP-IIand54-ballW-BGA (x16only) * OperatingTemperatureRange: Commercial:0oC to +70oC Industrial:-40oCto+85oC Automotive,A1:-40oCto+85oC 3.3V 3.3V SEPTEMBER 2009 OVERVIEW ISSI's512MbSynchronousDRAMachieveshigh-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The512MbSDRAMisorganizedasfollows. IS42S86400B 16Mx8x4Banks 54-pinTSOPII IS42/45S16320B 8Mx16x4Banks 54-pinTSOPII 54-ballW-BGA KEY TIMING PARAMETERS Parameter ClkCycleTime CASLatency=3 CASLatency=2 ClkFrequency CASLatency=3 CASLatency=2 AccessTimefromClock CASLatency=3 CASLatency=2 -6 6 10 166 100 5.4 6 -7 7 10 143 100 5.4 6 -75E - 7.5 - 133 - 5.5 Unit ns ns Mhz Mhz ns ns Copyright (c) 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 1 IS42S86400B, IS42/45S16320B DEVICE OVERVIEW The 512Mb SDRAM is a high speed CMOS, dynamic random-accessmemorydesignedtooperatein3.3VVdd and3.3VVddq memorysystemscontaining536,870,912 bits.Internallyconfiguredasaquad-bankDRAMwitha synchronousinterface.Each134,217,728-bitbankisorganizedas8,192rowsby1024columnsby16bits.Each ofthex8's134,217,728-bitbanksisorganizedas8,192 rowsby2048columnsby8bits. The512MbSDRAMincludesanAUTOREFRESHMODE, and a power-saving, power-down mode. All signals are registeredonthepositiveedgeoftheclocksignal,CLK. AllinputsandoutputsareLVTTLcompatible. The512MbSDRAMhastheabilitytosynchronouslyburst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during burst access. A self-timed row precharge initiated at the end of the burst sequenceisavailablewiththeAUTOPRECHARGEfunction enabled. Precharge one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-access operation. SDRAM read and write accesses are burst oriented starting at a selected location and continuing for a programmed number of locations in a programmed sequence. The registration of an ACTIVE command begins accesses, followedbyaREADorWRITEcommand.TheACTIVE command in conjunction with address bits registered are used to select the bank and row to be accessed (BA0, BA1selectthebank;A0-A12selecttherow).TheREAD or WRITE commands in conjunction with address bits registered are used to select the starting column location for the burst access. ProgrammableREADorWRITEburstlengthsconsistof 1,2,4and8locationsorfullpage,withaburstterminate option. FUNCTIONAL BLOCK DIAGRAM (FOR 8MX16X4 BANKS SHOWN) CLK CKE CS RAS CAS WE DQML DQMH 16 2 COMMAND DECODER & CLOCK GENERATOR DATAIN BUFFER 16 MODE REGISTER 13 REFRESH CONTROLLER DQ0-15 SELF REFRESH CONTROLLER A10 A12 A11 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 BA0 BA1 16 DATAOUT BUFFER VDD/VDDQ Vss/VssQ 16 REFRESH COUNTER 8192 8192 8192 8192 ROWDECODER MULTIPLEXER 13 MEMORYCELL ARRAY 13 ROW ADDRESS LATCH 13 ROW ADDRESS BUFFER BANK 0 SENSEAMPI/OGATE COLUMN ADDRESSLATCH 10 1024 (x16) BANKCONTROLLOGIC BURSTCOUNTER COLUMN ADDRESSBUFFER COLUMNDECODER 10 2 Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 IS42S86400B, IS42/45S16320B PIN CONFIGURATIONS 54 pin TSOP - Type II for x8 VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC VDD NC WE CAS RAS CS BA0 BA1 A10 A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC VSS NC DQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 VSS PIN DESCRIPTIONS A0-A12 A0-A9, A11 BA0,BA1 DQ0toDQ7 CLK CKE CS RAS CAS RowAddressInput Column Address Input BankSelectAddress DataI/O SystemClockInput ClockEnable Chip Select RowAddressStrobeCommand Column Address Strobe Command WE DQM Vdd Vss Vddq Vssq NC WriteEnable DataInput/OutputMask Power Ground PowerSupplyforI/OPin GroundforI/OPin NoConnection Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 3 IS42S86400B, IS42/45S16320B PIN CONFIGURATIONS 54 pin TSOP - Type II for x16 VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD DQML WE CAS RAS CS BA0 BA1 A10 A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS NC DQMH CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 VSS PIN DESCRIPTIONS A0-A12 A0-A9 BA0,BA1 DQ0toDQ15 CLK CKE CS RAS CAS RowAddressInput Column Address Input BankSelectAddress DataI/O SystemClockInput ClockEnable Chip Select RowAddressStrobeCommand Column Address Strobe Command WE DQML DQMH Vdd Vss Vddq Vssq NC WriteEnable x16LowerByte,Input/OutputMask x16UpperByte,Input/OutputMask Power Ground PowerSupplyforI/OPin GroundforI/OPin NoConnection 4 Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 IS42S86400B, IS42/45S16320B PIN CONFIGURATION 54-ball W-BGA for x16 (TopView)(11.00mmx13.00mmBody,0.8mmBallPitch) packagecode:B 1 2 3 4 5 6 7 8 9 A B C D E F G H J VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSS CKE A9 A6 A4 VDDQ DQ0 VDD VSSQ DQ2 DQ1 VDDQ DQ4 DQ3 VSSQ DQ6 DQ5 VDD DQML DQ7 CAS BA0 A0 A3 RAS BA1 A1 A2 WE CS A10 VDD DQMH CLK A12 A8 VSS A11 A7 A5 PIN DESCRIPTIONS A0-A12 A0-A9 BA0,BA1 DQ0toDQ15 CLK CKE CS RAS CAS RowAddressInput Column Address Input BankSelectAddress DataI/O SystemClockInput ClockEnable Chip Select RowAddressStrobeCommand Column Address Strobe Command WE DQML DQMH Vdd Vss Vddq Vssq NC WriteEnable x16LowerByteInput/OutputMask x16UpperByteInput/OutputMask Power Ground PowerSupplyforI/OPin GroundforI/OPin NoConnection Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 5 IS42S86400B, IS42/45S16320B PIN FUNCTIONS Symbol A0-A12 Type InputPin Function (In Detail) AddressInputs:A0-A12aresampledduringtheACTIVEcommand(row-address A0-A12)andREAD/WRITEcommand(columnaddressA0-A9(x16);A0-A9,A11 (x8);withA10definingautoprecharge)toselectonelocationoutofthememory arrayintherespectivebank.A10issampledduringaPRECHARGEcommandto determineifallbanksaretobeprecharged(A10HIGH)orbankselectedbyBA0, BA1(LOW).Theaddressinputsalsoprovidetheop-codeduringaLOADMODE REGISTERcommand. BankSelectAddress:BA0andBA1defineswhichbanktheACTIVE,READ,WRITE orPRECHARGEcommandisbeingapplied. CAS, in conjunction with the RAS and WE, forms the device command. See the "CommandTruthTable"fordetailsondevicecommands. TheCKEinputdetermineswhethertheCLKinputisenabled.Thenextrisingedge oftheCLKsignalwillbevalidwhenisCKEHIGHandinvalidwhenLOW.WhenCKE isLOW,thedevicewillbeineitherpower-downmode,clocksuspendmode,orself refresh mode. CKEisan asynchronous input. CLKisthemasterclockinputforthisdevice.ExceptforCKE,allinputstothisdevice areacquiredinsynchronizationwiththerisingedgeofthispin. TheCS input determines whether command input is enabled within the device. Command input is enabled when CSisLOW,anddisabledwithCSisHIGH.The device remains in the previous state when CSisHIGH. DQMLandDQMHcontrolthelowerandupperbytesoftheI/Obuffers.Inread mode,DQMLandDQMHcontroltheoutputbuffer.WhenDQMLorDQMHisLOW,the correspondingbufferbyteisenabled,andwhenHIGH,disabled.Theoutputsgoto theHIGHimpedancestatewhenDQML/DQMHisHIGH.Thisfunctioncorrespondsto OEinconventionalDRAMs.Inwritemode,DQMLandDQMHcontroltheinputbuffer. WhenDQMLorDQMHisLOW,thecorrespondingbufferbyteisenabled,anddata canbewrittentothedevice.WhenDQMLorDQMHisHIGH,inputdataismasked andcannotbewrittentothedevice.ForIS42/45S16320Bonly. ForIS42S86400Bonly. DataontheDataBusislatchedonDQpinsduringWritecommands,andbufferedfor outputafterReadcommands. RAS, in conjunction with CAS and WE, forms the device command. See the "CommandTruthTable"itemfordetailsondevicecommands. WE, in conjunction with RAS and CAS, forms the device command. See the "CommandTruthTable"itemfordetailsondevicecommands. Vddq is the output buffer power supply. Vdd is the device internal power supply. Vssq is the output buffer ground. Vss is the device internal ground. BA0,BA1 CAS CKE InputPin InputPin InputPin CLK CS InputPin InputPin DQML, DQMH InputPin DQM DQ0-DQ7 (x8)or DQ0-DQ15(x16) RAS WE Vddq Vdd Vssq Vss InputPin Input/Output InputPin InputPin P owerSupplyPin P owerSupplyPin P owerSupplyPin P owerSupplyPin 6 Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 IS42S86400B, IS42/45S16320B GENERAL DESCRIPTION READ TheREADcommandselectsthebankfromBA0,BA1inputs and starts a burst read access to an active row. Inputs A0-A9(x16);A0-A9,A11(x8)providesthestartingcolumn location.WhenA10isHIGH,thiscommandfunctionsasan AUTOPRECHARGEcommand.Whentheautoprecharge is selected, the row being accessed will be precharged at theendoftheREADburst.Therowwillremainopenfor subsequentaccesseswhenAUTOPRECHARGEisnot selected.DQ'sreaddataissubjecttothelogiclevelon the DQM inputs two clocks earlier.When a given DQM signalwasregisteredHIGH,thecorrespondingDQ'swill be High-Z two clocks later. DQ's will provide valid data whentheDQMsignalwasregisteredLOW. PRECHARGEfunctioninconjunctionwithaspecificREAD orWRITEcommand.ForeachindividualREADorWRITE command, auto precharge is either enabled or disabled. AUTOPRECHARGEdoesnotapplyexceptinfull-page burst mode. Upon completion of the READ or WRITE burst, a precharge of the bank/row that is addressed is automatically performed. AUTO REFRESH COMMAND ThiscommandexecutestheAUTOREFRESHoperation. Therowaddressandbanktoberefreshedareautomatically generatedduringthisoperation. Thestipulatedperiod(trc)is requiredforasinglerefreshoperation,andnoothercommandscanbeexecutedduringthisperiod. Thiscommand isexecutedatleast8192timesforevery64ms.Duringan AUTOREFRESHcommand,addressbitsare"Don'tCare". ThiscommandcorrespondstoCBRAuto-refresh. WRITE A burst write access to an active row is initiated with the WRITEcommand.BA0,BA1inputsselectsthebank,and the starting column location is provided by inputs A0-A9 (x16);A0-A9,A11(x8).WhetherornotAUTO-PRECHARGE is used is determined by A10. Therowbeingaccessedwillbeprechargedattheendof theWRITE burst, if AUTO PRECHARGE is selected. If AUTOPRECHARGEisnotselected,therowwillremain openforsubsequentaccesses. A memory array is written with corresponding input data onDQ'sandDQMinputlogiclevelappearingatthesame time.DatawillbewrittentomemorywhenDQMsignalis LOW.WhenDQMisHIGH,thecorrespondingdatainputs willbeignored,andaWRITEwillnotbeexecutedtothat byte/column location. BURST TERMINATE The BURSTTERMINATE command forcibly terminates the burst read and write operations by truncating either fixed-length or full-page bursts and the most recently registeredREADorWRITEcommandpriortotheBURST TERMINATE. COMMAND INHIBIT COMMANDINHIBITpreventsnewcommandsfrombeing executed.Operationsinprogressarenotaffected,apart fromwhethertheCLKsignalisenabled NO OPERATION WhenCSislow,theNOPcommandpreventsunwanted commands from being registered during idle or wait states. PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. BA0,BA1canbeusedtoselectwhichbankisprecharged or they are treated as "Don't Care". A10 determined whether one or all banks are precharged. After executing this command, the next command for the selected bank(s)isexecutedafterpassageoftheperiodtRP, which istheperiodrequiredforbankprecharging.Onceabank has been precharged, it is in the idle state and must be activatedpriortoanyREADorWRITEcommandsbeing issued to that bank. LOAD MODE REGISTER DuringtheLOADMODEREGISTERcommandthemode registerisloadedfromA0-A12.Thiscommandcanonly be issued when all banks are idle. ACTIVE COMMAND When the ACTIVE COMMAND is activated, BA0, BA1 inputs selects a bank to be accessed, and the address inputsonA0-A12selectstherow.UntilaPRECHARGE command is issued to the bank, the row remains open for accesses. AUTO PRECHARGE TheAUTOPRECHARGEfunctionensuresthattheprecharge is initiated at the earliest valid stage within a burst. Thisfunctionallowsforindividual-bankprechargewithout requiringanexplicitcommand.A10toenabletheAUTO Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 7 IS42S86400B, IS42/45S16320B COMMAND TRUTH TABLE CKE Function n-1 Devicedeselect(DESL) H Nooperation(NOP) H Burststop(BST) H Read H Readwithautoprecharge H Write H Writewithautoprecharge H Bankactivate(ACT) H Prechargeselectbank(PRE) H Prechargeallbanks(PALL) H CBRAuto-Refresh(REF) H Self-Refresh(SELF) H Moderegisterset(MRS) H n x x x x x x x x x x H L x CS H L L L L L L L L L L L L RAS x H H H H H H L L L L L L CAS x H H L L L L H H H L L L WE x H L H H L L H L L H H L BA1 x x x V V V V V V x x x L BA0 x x x V V V V V V x x x L A10 x x x L H L H V L H x x L A12, A11 A9 - A0 x x x V V V V V x x x x V Note:H=Vih,L=Vilx=Vih or Vil,V=ValidData. DQM TRUTH TABLE Function Datawrite/outputenable Datamask/outputdisable Upperbytewriteenable/outputenable Lowerbytewriteenable/outputenable Upperbytewriteinhibit/outputdisable Lowerbytewriteinhibit/outputdisable Note:H=Vih,L=Vilx=Vih or Vil,V=ValidData. CKE n-1 H H H H H H n x x x x x x DQMH L H L x H x DQML L H x L x H 8 Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 IS42S86400B, IS42/45S16320B CKE TRUTH TABLE CurrentState/Function ActivatingClocksuspendmodeentry AnyClocksuspendmode Clocksuspendmodeexit AutorefreshcommandIdle(REF) SelfrefreshentryIdle(SELF) PowerdownentryIdle Selfrefreshexit Powerdownexit Note:H=Vih,L=Vilx=Vih or Vil,V=ValidData. CKE n-1 n H L L L L H H H H L H L L H L H L H CS x x x L L x L H x RAS x x x L L x H x x CAS x x x L L x H x x WE x x x H H x H x x Address x x x x x x x x x Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 9 IS42S86400B, IS42/45S16320B FUNCTIONAL TRUTH TABLE Current State Idle RowActive Read Write CS H L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L RAS CAS X H H H H L L L L X H H H H L L L L X H H H H L L L L X H H H H L L L L X H H L L H H L L X H H L L H H L L X H H L L H H L L X H H L L H H L L WE X H L H L H L H L X H L H L H L H L X H L H L H L H L X H L H L H L H L Address X X X BA,CA,A10 A,CA,A10 BA,RA BA,A10 X OC,BA1=L X X X BA,CA,A10 BA,CA,A10 BA,RA BA,A10 X OC,BA X X X BA,CA,A10 BA,CA,A10 BA,RA BA,A10 X OC,BA X X X BA,CA,A10 BA,CA,A10 BA,RA BA,A10 X OC,BA Command DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA RAACT PRE/PALL REF/SELF MRS Action NoporPowerDown(2) NoporPowerDown(2) NoporPowerDown ILLEGAL(3) ILLEGAL(3) Rowactivating Nop AutorefreshorSelf-refresh(4) Moderegisterset Nop Nop Nop Beginread(5) Beginwrite(5) ILLEGAL(3) Precharge Prechargeallbanks(6) ILLEGAL ILLEGAL Continuebursttoendto Rowactive ContinuebursttoendRow Rowactive Burststop,Rowactive Terminateburst, begin new read (7) Terminateburst, begin write (7,8) ILLEGAL(3) Terminateburst Precharging ILLEGAL ILLEGAL Continuebursttoend Writerecovering Continuebursttoend Writerecovering Burststop,Rowactive Terminateburst,startread: DetermineAP(7,8) Terminateburst,newwrite: DetermineAP(7) ILLEGAL(3) TerminateburstPrecharging(9) ILLEGAL ILLEGAL Note:H=Vih,L=Vilx=Vih or Vil,V=ValidData,BA=BankAddress,CA+ColumnAddress,RA=RowAddress,OC=Op-Code 10 Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 IS42S86400B, IS42/45S16320B FUNCTIONAL TRUTH TABLE Continued: Current State Readwithauto Precharging WritewithAuto Precharge Precharging RowActivating CS H L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L RAS CAS x H H H H L L L L x H H H H L L L L x H H H H L L L L x H H H H L L L L x H H L L H H L L x H H L L H H L L x H H L L H H L L x H H L L H H L L WE x H L H L H L H L x H L H L H L H L x H L H L H L H L x H L H L H L H L Address x x x BA,CA,A10 BA,CA,A10 BA,RA BA,A10 x OC,BA x x x BA,CA,A10 BA,CA,A10 BA,RA BA,A10 x OC,BA x x x BA,CA,A10 BA,CA,A10 BA,RA BA,A10 x OC,BA x x x BA,CA,A10 BA,CA,A10 BA,RA BA,A10 x OC,BA Command DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Action Continuebursttoend,Precharge Continuebursttoend,Precharge ILLEGAL ILLEGAL(11) ILLEGAL(11) ILLEGAL(3) ILLEGAL(11) ILLEGAL ILLEGAL Continuebursttoend,Write recoveringwithautoprecharge Continuebursttoend,Write recovering with auto precharge ILLEGAL ILLEGAL(11) ILLEGAL(11) ILLEGAL(3,11) ILLEGAL(3,11) ILLEGAL ILLEGAL Nop,EnteridleaftertRP Nop,EnteridleaftertRP Nop,EnteridleaftertRP ILLEGAL(3) ILLEGAL(3) ILLEGAL(3) NopEnteridleaftertRP ILLEGAL ILLEGAL Nop,EnterbankactiveaftertRCD Nop,EnterbankactiveaftertRCD Nop,EnterbankactiveaftertRCD ILLEGAL(3) ILLEGAL(3) ILLEGAL(3,9) ILLEGAL(3) ILLEGAL ILLEGAL Note:H=Vih,L=Vilx=Vih or Vil,V=ValidData,BA=BankAddress,CA+ColumnAddress,RA=RowAddress,OC=Op-Code Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 11 IS42S86400B, IS42/45S16320B FUNCTIONAL TRUTH TABLE Continued: Current State WriteRecovering WriteRecovering withAuto Precharge Refresh ModeRegister Accessing CS H L L L L L L L L H L L L L L L L L H L L L L L L L H L L L L RAS CAS x H H H H L L L L x H H H H L L L L x H H H L L L L x H H H L x H H L L H H L L x H H L L H H L L x H L L H H L L x H H L x WE x H L H L H L H L x H L H L H L H L x x H L H L H L x H L x x Address x x x BA,CA,A10 BA,CA,A10 BA,RA BA,A10 x OC,BA x x x BA,CA,A10 BA,CA,A10 BA,RA BA,A10 x OC,BA x x BA,CA,A10 BA,CA,A10 BA,RA BA,A10 x OC,BA x x x BA,CA,A10 BA,RA Command DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP/BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/WRITE Action Nop,EnterrowactiveaftertDPL Nop,EnterrowactiveaftertDPL Nop,EnterrowactiveaftertDPL Beginread(8) Beginnewwrite ILLEGAL(3) ILLEGAL(3) ILLEGAL ILLEGAL Nop,EnterprechargeaftertDPL Nop,EnterprechargeaftertDPL Nop,EnterrowactiveaftertDPL ILLEGAL(3,8,11) ILLEGAL(3,11) ILLEGAL(3,11) ILLEGAL(3,11) ILLEGAL ILLEGAL Nop,EnteridleaftertRC Nop,EnteridleaftertRC ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop,Enteridleafter2clocks Nop,Enteridleafter2clocks ILLEGAL ILLEGAL ACT/PRE/PALL ILLEGAL REF/MRS Note:H=Vih,L=Vilx=Vih or Vil,V=ValidData,BA=BankAddress,CA+ColumnAddress,RA=RowAddress,OC=Op-Code Notes: 1.AllentriesassumethatCKEisactive(CKEn-1=CKEn=H). 2.Ifbothbanksareidle,andCKEisinactive(Low),thedevicewillenterPowerDownmode.AllinputbuffersexceptCKEwillbe disabled. 3.Illegaltobankinspecifiedstates;FunctionmaybelegalinthebankindicatedbyBankAddress(BA),dependingonthestateof that bank. 4.Ifbothbanksareidle,andCKEisinactive(Low),thedevicewillenterSelf-Refreshmode.AllinputbuffersexceptCKEwillbe disabled. 5.IllegaliftRCDisnotsatisfied. 6.IllegaliftRASisnotsatisfied. 7.Mustsatisfyburstinterruptcondition. 8.Mustsatisfybuscontention,busturnaround,and/orwriterecoveryrequirements. 9.Mustmaskprecedingdatawhichdon'tsatisfytDPL. 10.IllegaliftRRDisnotsatisfied. 11. Illegal for single bank, but legal for other banks. 12 Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 IS42S86400B, IS42/45S16320B CKE RELATED COMMAND TRUTH TABLE(1) Current State Operation Self-Refresh(S.R.) INVALID,CLK(n-1)wouldexitS.R. Self-RefreshRecovery(2) Self-RefreshRecovery(2) Illegal Illegal MaintainS.R. Self-RefreshRecoveryIdleAftertrc Idle After trc Illegal Illegal Beginclocksuspendnextcycle(5) Beginclocksuspendnextcycle(5) Illegal Illegal Exit clock suspend next cycle(2) Maintainclocksuspend Power-Down(P.D.) INVALID,CLK(n-1)wouldexitP.D. EXITP.D.-->Idle(2) Maintainpowerdownmode AllBanksIdle RefertooperationsinOperativeCommandTable RefertooperationsinOperativeCommandTable RefertooperationsinOperativeCommandTable Auto-Refresh RefertooperationsinOperativeCommandTable RefertooperationsinOperativeCommandTable RefertooperationsinOperativeCommandTable RefertooperationsinOperativeCommandTable Self-Refresh(3) RefertooperationsinOperativeCommandTable Power-Down(3) Anystate RefertooperationsinOperativeCommandTable otherthan Beginclocksuspendnextcycle(4) listedabove Exitclocksuspendnextcycle Maintainclocksuspend CKE n-1 H L L L L L H H H H H H H H L L H L L H H H H H H H H H H L H H L L n X H H H H L H H H H L L L L H L X H L H H H H H L L L L L X H L H L CS X H L L L X H L L L H L L L X X X X X H L L L L H L L L L X X X X X RAS X X H H L X X H H L X H H L X X X X X X H L L L X H L L L X X X X X CAS X X H L X X X H L X X H L X X X X X X X X H L L X X H L L X X X X X WE X X X X X X X X X X X X X X X X X X X X X X H L X X X H L X X X X X Address X X X X X X X X X X X X X X X X -- X X -- -- -- X Op-Code -- -- -- X Op-Code X X X X X Notes: 1.H:Highlevel,L:lowlevel,X:Highorlowlevel(Don'tcare). 2.CKELowtoHightransitionwillre-enableCLKandotherinputsasynchronously.Aminimumsetup timemustbesatisfiedbeforeanycommandotherthanEXIT. 3.PowerdownandSelfrefreshcanbeenteredonlyfromthebothbanksidlestate. 4.MustbelegalcommandasdefinedinOperativeCommandTable. 5.Illegaliftxsr is not satisfied. Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 13 IS42S86400B, IS42/45S16320B STATE DIAGRAM Self Refresh SELF SELFexit Mode Register Set MRS IDLE REF CBR(Auto) Refresh CKE CKE ACT Power Down Row Active BST CKE CKE Read BST Active Power Down ith rge Write Au to Re w rite W to WRITE SUSPEND Au CKE WRITE CKE Pr ec Write ha Read CKE READ CKE ith w ad arge h ec Pr Read Write READ SUSPEND POWER ON Precharge Precharge PR E( Pr ec ha rge WRITEA SUSPEND ter WRITEA mi CKE CKE na tio RR E( Pre arg ch et ina erm tio n) n) CKE READA CKE READA SUSPEND Automaticsequence ManualInput 14 Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 IS42S86400B, IS42/45S16320B ABSOLUTE MAXIMUM RATINGS(1) Symbol Vdd max Vddq max Vin Vout Pd max Ics Topr Tstg Parameters Rating MaximumSupplyVoltage -0.5to+4.6 MaximumSupplyVoltageforOutputBuffer -0.5to+4.6 InputVoltage -0.5toVdd+0.5 OutputVoltage -1.0toVddq+0.5 AllowablePowerDissipation 1 outputShortedCurrent 50 operatingTemperature Com. 0 to +70 Auto/Ind. -40to+85 StorageTemperature -65to+150 Unit V V V V W mA C C Notes: 1. StressgreaterthanthoselistedunderABSOLUTEMAXIMUMRATINGSmaycausepermanentdamageto thedevice.Thisisastressratingonlyandfunctionaloperationofthedeviceattheseoranyotherconditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. All voltages are referenced to Vss. DC RECOMMENDED OPERATING CONDITIONS Symbol Vdd Vddq Vih(1) Vil(2) Note: 1. Vih (overshoot): Vih (max)=Vddq +1.2V (pulse width < 3ns). 2. Vil (undershoot): Vih (min)=-1.2V (pulse width < 3ns). 3. AllvoltagesarereferencedtoVss. Parameter SupplyVoltage I/OSupplyVoltage InputHighVoltage InputLowVoltage Min. 3.0 3.0 2.0 -0.3 Typ. 3.3 3.3 -- -- Max. 3.6 3.6 Vddq +0.3 +0.8 Unit V V V V CAPACITANCE CHARACTERISTICS (AtTa=0to+25C,Vdd=Vddq =3.30.3V) Symbol Cin1 Cin2 Ci/o Parameter InputCapacitance:CLK InputCapacitance:Allotherinputpins DataInput/OutputCapacitance:DQS Min. 2.5 2.5 4.0 Max. 3.5 3.8 6.0 Unit pF pF pF Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 15 IS42S86400B, IS42/45S16320B DC ELECTRICAL CHARACTERISTICS 1 (RecommendedOperationConditionsunlessotherwisenoted.) Symbol idd1 (1) idd2p idd2ps idd2n (2) Idd2ns idd3n (2) Idd3ns Idd3p Idd3ps idd4 idd5 idd6 Parameter OperatingCurrent PrechargeStandbyCurrent (InPower-DownMode) PrechargeStandbyCurrent (InPower-DownMode) PrechargeStandbyCurrent (InNonPower-DownMode) PrechargeStandbyCurrent (InNonPower-DownMode) Active Standby Current (InNonPower-DownMode) Active Standby Current (InNonPower-DownMode) ActiveStandbyCurrent (Power-DownMode) ActiveStandbyCurrent (Power-DownMode) OperatingCurrent Auto-RefreshCurrent Self-RefreshCurrent Test Condition Onebankactive,CL=3,BL=1, tclk=tclk(min),trc=trc(min) CKE Vil (max),tck=15ns CKE Vil (max),CLK Vil (max) CS Vcc-0.2V,CKE Vih (min) tck=15ns CS Vcc-0.2V,CKE Vih (min)or CKE Vil (max),Allinputsstable CS Vcc-0.2V,CKE Vih (min) tck=15ns CS Vcc-0.2V,CKE Vih (min)or CKE Vil (max),Allinputsstable CKE Vil (max),tck=15ns CKE Vil (max),CLK Vil (max) Allbanksactive,BL=4,CL=3, tck=tck(min) trc=trc(min),tclk=tclk(min) CKE 0.2V -6 160 4 4 35 20 55 30 6 6 180 350 6 -7 140 4 4 35 20 55 30 6 6 150 300 6 -75E 160 4 4 35 20 55 30 6 6 180 350 6 Unit mA mA mA mA mA mA mA mA mA mA mA mA Notes: 1. Idd (max)isspecifiedattheoutputopencondition. 2. Inputsignalsarechangedonetimeduring30ns. DC ELECTRICAL CHARACTERISTICS 2 (RecommendedOperationConditionsunlessotherwisenoted.) Symbol iil iol Voh Vol Parameter InputLeakageCurrent OutputLeakageCurrent OutputHighVoltageLevel OutputLowVoltageLevel Test Condition 0V Vin Vcc,withpinsotherthan the tested pin at 0V Outputisdisabled,0V Vout Vcc, Ioh=-2mA Iol=2mA Min -5 -5 2.4 -- Max 5 5 -- 0.4 Unit A A V V 16 Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 IS42S86400B, IS42/45S16320B AC ELECTRICAL CHARACTERISTICS (1,2,3) -6 Symbol tck3 tck2 tac3 tac2 tchi tcl toh3 toh2 tlz thz3 thz2 tds tdh tas tah tcks tckh tcs tch trc tras trp trcd trrd tdpl tdal tmrd tdde txsr tt tref CASLatency=3 CASLatency=2 AccessTimeFromCLK CASLatency=3 CASLatency=2 CLKHIGHLevelWidth CLKLOWLevelWidth OutputDataHoldTime CASLatency=3 CAS Latency=2 OutputLOWImpedanceTime OutputHIGHImpedanceTime OutputHIGHImpedanceTime InputDataSetupTime(2) (2) InputDataHoldTime AddressSetupTime(2) (2) AddressHoldTime (2) CKESetupTime CKEHoldTime(2) CommandSetupTime(CS, RAS, CAS, WE,DQM)(2) CommandHoldTime(CS, RAS, CAS, WE,DQM)(2) CommandPeriod(REFtoREF/ACTtoACT) CommandPeriod(ACTtoPRE) CommandPeriod(PREtoACT) ActiveCommandToRead/WriteCommandDelayTime CommandPeriod(ACT[0]toACT[1]) InputDataToPrecharge CommandDelaytime InputDataToActive/Refresh CommandDelaytime(DuringAuto-Precharge) ModeRegisterProgramTime PowerDownExitSetupTime ExitSelf-RefreshtoActiveTime TransitionTime RefreshCycleTime(8192) Parameter ClockCycleTime Min. 6 10 -- -- 2.5 2.5 2.7 2.7 0 2.7 2.7 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 60 42 18 18 12 12 30 12 6 66 0.3 -- Max. -- -- 5.4 6 -- -- -- -- -- 5.4 6 -- -- -- -- -- -- -- -- -- 100K -- -- -- -- -- -- -- -- 1.2 64 Min. 7 10 -- -- 2.5 2.5 2.7 2.7 0 2.7 2.7 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 70 49 20 20 14 14 35 14 7 77 0.3 -- -7 Max. -- -- 5.4 6 -- -- -- -- -- 5.4 6 -- -- -- -- -- -- -- -- -- 100K -- -- -- -- -- -- -- -- 1.2 64 -75E Min. -- 7.5 -- -- 2.5 2.5 2.7 2.7 0 -- 2.7 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 60 45 15 15 15 15 30 15 7.5 67.5 0.3 -- Max. -- -- -- 5.5 -- -- -- -- -- -- 5.5 -- -- -- -- -- -- -- -- -- 100K -- -- -- -- -- -- -- -- 1.2 64 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms Notes: 1. Thepower-onsequencemustbeexecutedbeforestartingmemoryoperation. 2. measured with tt =1ns.Ifclockrisingtimeislongerthan1ns,(tr/2-0.5)nsshouldbeaddedtotheparameter. 3.Thereferencelevelis1.4Vwhenmeasuringinputsignaltiming.RiseandfalltimesaremeasuredbetweenVih(min.)andVil (max). Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 17 IS42S86400B, IS42/45S16320B OPERATING FREQUENCY / LATENCY RELATIONSHIPS SYMBOL PARAMETER -- -- tcac trcd trac trc tras trp trrd tccd tdpl tdal trbd twbd trql twdl tpql tqmd tdmd tmrd ClockCycleTime OperatingFrequency CASLatency ActiveCommandToRead/WriteCommandDelayTime RASLatency(trcd + tcac) CommandPeriod(REFtoREF/ACTtoACT) CommandPeriod(ACTtoPRE) CommandPeriod(PREtoACT) CommandPeriod(ACT[0]toACT[1]) ColumnCommandDelayTime (READ,READA,WRIT,WRITA) InputDataToPrechargeCommandDelayTime InputDataToActive/RefreshCommandDelayTime (DuringAuto-Precharge) BurstStopCommandToOutputinHIGH-ZDelayTime -6 CASLatency=3 CASLatency=2 CASLatency=3 CASLatency=2 CASLatency=3 CASLatency=2 CASLatency=3 CASLatency=2 CASLatency=3 CASLatency=2 CASLatency=3 CASLatency=2 CASLatency=3 CASLatency=2 CASLatency=3 CASLatency=2 6 10 166 100 3 2 3 2 6 4 10 6 7 5 3 2 2 1 2 5 4 3 2 0 3 2 0 -2 -1 2 0 2 -7 7 10 143 100 3 2 3 2 6 4 10 7 7 5 3 2 2 1 2 5 4 3 2 0 3 2 0 -2 -1 2 0 2 -75E -- 7.5 -- 133 -- 2 -- 2 -- 4 -- 8 -- 6 -- 2 2 1 2 -- 4 -- 2 0 -- 2 0 -- -1 2 0 2 UNITS ns ns MHz MHz cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle CASLatency=3 CASLatency=2 CASLatency=3 CASLatency=2 (Read) BurstStopCommandToInputinInvalidDelayTime (Write) PrechargeCommandToOutputinHIGH-ZDelayTime (Read) PrechargeCommandToInputinInvalidDelayTime (Write) LastOutputToAuto-PrechargeStartTime(Read) CASLatency=3 CASLatency=2 CASLatency=3 CASLatency=2 DQMToOutputDelayTime(Read) DQMToInputDelayTime(Write) ModeRegisterSetToCommandDelayTime 18 Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 IS42S86400B, IS42/45S16320B AC TEST CONDITIONS Input Load tCK tCHI 3.0V Output Load tCL 1.4V CLK 1.4V 0V 3.0V tCS tCH Z = 50 Output 50 pF 50 INPUT 1.4V 0V tOH OUTPUT 1.4V tAC 1.4V AC TEST CONDITIONS Parameter ACInputLevels InputRiseandFallTimes InputTimingReferenceLevel OutputTimingMeasurementReferenceLevel Rating 0Vto3.0V 1ns 1.4V 1.4V Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 19 IS42S86400B, IS42/45S16320B FUNCTIONAL DESCRIPTION The512MbSDRAMsarequad-bankDRAMswhichoperate at3.3Vandincludeasynchronousinterface(allsignals are registered on the positive edge of the clock signal, CLK).Eachofthe134,217,728-bitbanksisorganizedas 8,192rowsby1024columnsby16bitsor8192rowsby 2048columnsby8bits. ReadandwriteaccessestotheSDRAMareburstoriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVEcommandwhichisthenfollowedbyaREADor WRITEcommand.Theaddressbitsregisteredcoincident withtheACTIVEcommandareusedtoselectthebank and row to be accessed (BA0andBA1selectthebank,A0A12 select the row). The address bits A0-A9 (x16); A0-A9, A11(x8)registeredcoincidentwiththeREADorWRITE command are used to select the starting column location for the burst access. Prior to normal operation, the SDRAM must be initialized.Thefollowingsectionsprovidedetailedinformation coveringdeviceinitialization,registerdefinition,command descriptions and device operation. Initialization SDRAMs must be powered up and initialized in a predefined manner. The512MbSDRAMisinitializedafterthepowerisapplied to Vdd and Vddq(simultaneously)andtheclockisstable withDQMHighandCKEHigh. A100sdelayisrequiredpriortoissuinganycommand other than a COMMANDINHIBIT or a NOP.TheCOMMAND INHIBITorNOPmaybeappliedduringthe100usperiodand should continue at least through the end of the period. WithatleastoneCOMMANDINHIBITorNOPcommand havingbeenapplied,aPRECHARGEcommandshould be applied once the 100s delay has been satisfied. All banksmustbeprecharged.Thiswillleaveallbanksinan idle state after which at least eight AUTOREFRESH cycles must be performed. After the AUTOREFRESH cycles are complete, the SDRAM is then ready for mode register programming. The mode register should be loaded prior to applying any operational command because it will power up in an unknown state. 20 Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 IS42S86400B, IS42/45S16320B INITIALIzE AND LOAD MODE REGISTER(1) T0 CLK tCK T1 Tn+1 tCH To+1 tCL Tp+1 Tp+2 Tp+3 tCKS tCKH CKE tCMH tCMS COMMAND DQM/ DQML, DQMH tAS tAH A0-A9, A11, A12 ALL BANKS A10 SINGLE BANK BA0, BA1 DQ T Power-up: VCC and CLK stable T = 200s Min. tRP Precharge all banks tRC AUTO REFRESH tRC AUTO REFRESH tMRD Program MODE REGISTER (2, 3, 4) DON'T CARE ALL BANKS CODE tAS tAH CODE tAS tAH CODE BANK ROW ROW NOP tCMH tCMS PRECHARGE tCMH tCMS AUTO REFRESH NOP AUTO REFRESH NOP Load MODE REGISTER NOP ACTIVE At least 8 Auto-Refresh Commands Notes: 1. If CSisHighatclockHightime,allcommandsappliedareNOP. 2.TheModeregistermaybeloadedpriortotheAuto-Refreshcyclesifdesired. 3.JEDECandPC100specifythreeclocks. 4.OutputsareguaranteedHigh-Zafterthecommandisissued. Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 21 IS42S86400B, IS42/45S16320B AUTO-REFRESH CYCLE T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/ DQML, DQMH A0-A9, A11, A12 ALL BANKS A10 SINGLE BANK BA0, BA1 DQ BANK(s) tAS tAH High-Z tRP tRC tRC DON'T CARE Notes: 1. CASlatency=2,3 tCK T1 tCL T2 tCH Tn+1 To+1 PRECHARGE NOP Auto Refresh NOP Auto Refresh NOP ACTIVE ROW ROW BANK 22 Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 IS42S86400B, IS42/45S16320B SELF-REFRESH CYCLE T0 CLK tCK tCKS tCKH CKE tCMS tCMH COMMAND DQM/ DQML, DQMH A0-A9, A11, A12 ALL BANKS A10 SINGLE BANK tAS tAH BA0, BA1 BANK PRECHARGE T1 tCH tCL T2 tCKS Tn+1 To+1 To+2 tRAS tCKS NOP Auto Refresh NOP NOP Auto Refresh DQ High-Z Precharge all active banks tRP Enter self refresh mode tXSR CLK stable prior to exiting Exit self refresh mode self refresh mode (Restart refresh time base) DON'T CARE Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 23 IS42S86400B, IS42/45S16320B REGISTER DEFINITION Mode Register The mode register is used to define the specific mode ofoperationoftheSDRAM.Thisdefinitionincludesthe selection of a burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in MODEREGISTERDEFINITION. ThemoderegisterisprogrammedviatheLOADMODE REGISTERcommandandwillretainthestoredinformation until it is programmed again or the device loses power. Mode register bits M0-M2 specify the burst length, M3 specifies the type of burst (sequentialorinterleaved),M4-M6 specifytheCASlatency,M7andM8specifytheoperating mode,M9specifiestheWRITEburstmode,andM10,M11, andM12arereservedforfutureuse. The mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiatingthesubsequentoperation.Violatingeitherofthese requirementswillresultinunspecifiedoperation. MODE REGISTER DEFINITION BA1 BA0 A12 A11 A10 (1) A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus (Ax) Mode Register (Mx) Reserved Burst Length M2 0 0 0 0 1 1 1 1 Burst Type M3 0 1 Latency Mode M6 M5 M4 0 0 0 0 1 1 1 1 Operating Mode M8 M7 00 ---- M6-M0 Defined -- Mode Standard Operation All Other States Reserved 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 CAS Latency Reserved Reserved 2 3 Reserved Reserved Reserved Reserved Type Sequential Interleaved M1 0 0 1 1 0 0 1 1 M0 0 1 0 1 0 1 0 1 M3=0 1 2 4 8 Reserved Reserved Reserved Full Page M3=1 1 2 4 8 Reserved Reserved Reserved Reserved Write Burst Mode M9 0 1 Mode Programmed Burst Length Single Location Access 1. To ensure compatibility with future devices, should program BA1, BA0, A12, A11, A10 = "0" 24 Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 IS42S86400B, IS42/45S16320B BURST LENGTH ReadandwriteaccessestotheSDRAMareburstoriented, with the burst length being programmable, as shown in MODEREGISTERDEFINITION.Theburstlengthdetermines the maximum number of column locations that can beaccessedforagivenREADorWRITEcommand.Burst lengthsof1,2,4or8locationsareavailableforboththe sequentialandtheinterleavedbursttypes,andafull-page burst is available for the sequential type.The full-page burstisusedinconjunctionwiththeBURSTTERMINATE command to generate arbitrary burst lengths. Reservedstatesshouldnotbeused,asunknownoperation or incompatibility with future versions may result. WhenaREADorWRITEcommandisissued,ablockof columnsequaltotheburstlengthiseffectivelyselected.All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary isreached.TheblockisuniquelyselectedbyA1-A9(x16) orA1-A9,A11(x8)whentheburstlengthissettotwo;by A2-A9(x16)orA1-A9,A11(x8)whentheburstlengthis settofour;andbyA3-A9(x16)orA1-A9,A11(x8)when theburstlengthissettoeight.Theremaining(leastsignificant)addressbit(s)is(are)usedtoselectthestarting locationwithintheblock.Full-pageburstswrapwithinthe page if the boundary is reached. BurstType Accesses within a given burst may be programmed to be eithersequentialorinterleaved;thisisreferredtoasthe bursttypeandisselectedviabitM3. Theorderingofaccesseswithinaburstisdeterminedby the burst length, the burst type and the starting column address,asshowninBURSTDEFINITIONtable. BURST DEFINITION Burst Length Starting Column Address A0 2 0 1 A1 A0 0 0 4 0 1 1 0 1 1 A2 A1 A0 0 0 0 0 0 1 0 1 0 8 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Full n=A0-A9(x16) Page n=A0-A9,A11(x8) (y) (location0-y) Order of Accesses Within a Burst Type = Sequential Type = Interleaved 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Cn,Cn+1,Cn+2 Cn+3,Cn+4... ...Cn-1, Cn... 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 NotSupported Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 25 IS42S86400B, IS42/45S16320B CAS Latency The CAS latency is the delay, in clock cycles, between the registrationofaREADcommandandtheavailabilityof thefirstpieceofoutputdata.Thelatencycanbesettotwoor three clocks. IfaREADcommandisregisteredatclockedgen,and the latency is m clocks, the data will be available by clock edge n + m.TheDQswillstartdrivingasaresultofthe clock edge one cycle earlier (n + m -1),andprovidedthat the relevant access times are met, the data will be valid by clock edge n + m.Forexample,assumingthattheclock cycle time is such that all relevant access times are met, ifaREADcommandisregisteredatT0andthelatency isprogrammedtotwoclocks,theDQs willstartdriving afterT1andthedatawillbevalidbyT2,asshowninCAS Latency diagrams.The Allowable Operating Frequency tableindicatestheoperatingfrequenciesatwhicheach CAS latency setting can be used. Reservedstatesshouldnotbeusedasunknownoperation or incompatibility with future versions may result. Operating Mode ThenormaloperatingmodeisselectedbysettingM7andM8 tozero;theothercombinationsofvaluesforM7andM8are reservedforfutureuseand/ortestmodes.Theprogrammed burstlengthappliestobothREADandWRITEbursts. Testmodesandreservedstatesshouldnotbeusedbecause unknown operation or incompatibility with future versions may result. Write Burst Mode WhenM9=0,theburstlengthprogrammedviaM0-M2 appliestobothREADandWRITEbursts;whenM9=1, theprogrammedburstlengthappliestoREADbursts,but writeaccessesaresingle-location(nonburst)accesses. CAS Latency Allowable Operating Frequency (MHz) Speed -6 -7 -75E CAS Latency = 2 100 100 133 CAS Latency = 3 166 143 -- CAS LATENCY T0 CLK T1 T2 T3 COMMAND DQ READ NOP tAC NOP DOUT tLZ CAS Latency - 2 tOH T0 CLK T1 T2 T3 T4 COMMAND DQ READ NOP NOP tAC NOP DOUT tLZ CAS Latency - 3 tOH DON'T CARE UNDEFINED 26 Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 IS42S86400B, IS42/45S16320B CHIP OPERATION BANK/ROW ACTIVATION Before any READ orWRITE commands can be issued toabankwithintheSDRAM,arowinthatbankmustbe "opened."ThisisaccomplishedviatheACTIVEcommand, which selects both the bank and the row to be activated (see ActivatingSpecificRowWithinSpecificBank). After opening a row (issuinganACTIVEcommand),aREAD orWRITEcommandmaybeissuedtothatrow,subjectto the trcdspecification.Minimumtrcd should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE commandonwhichaREADorWRITEcommandcanbe entered.Forexample,atrcdspecificationof15nswitha 143MHzclock(7nsperiod)resultsin2.14clocks,rounded to3.Thisisreflectedinthefollowingexample,whichcoversanycasewhere2<[trcd(MIN)/tck] 3.(Thesame procedure is used to convert other specification limits from timeunitstoclockcycles). AsubsequentACTIVEcommandtoadifferentrowinthe same bank can only be issued after the previous active rowhasbeen"closed"(precharged).Theminimumtime interval between successive ACTIVE commands to the same bank is defined by trc. AsubsequentACTIVEcommandtoanotherbankcanbe issued while the first bank is being accessed, which results inareductionoftotalrow-accessoverhead.Theminimum timeintervalbetweensuccessiveACTIVEcommandsto different banks is defined by trrd. ACTIVATING SPECIFIC ROW WITHIN SPECIFIC BANK CLK HIGH CKE CS RAS CAS WE A0-A12 BA0, BA1 ROW ADDRESS BANK ADDRESS EXAMPLE: MEETING TRCD (MIN) WHEN 2 < [TRCD (MIN)/TCK] 3 T0 CLK T1 T2 T3 T4 COMMAND ACTIVE NOP tRCD NOP READ or WRITE DON'T CARE Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 27 IS42S86400B, IS42/45S16320B READS READ bursts are initiated with a READ command, as shownintheREADCOMMANDdiagram. Thestartingcolumnandbankaddressesareprovidedwith theREADcommand,andautoprechargeiseitherenabledor disabled for that burst access. If auto precharge is enabled, the row being accessed is precharged at the completion of theburst.ForthegenericREADcommandsusedinthefollowing illustrations, auto precharge is disabled. DuringREADbursts,thevaliddata-outelementfromthe starting column address will be available following the CASlatencyaftertheREADcommand.Eachsubsequent data-out element will be valid by the next positive clock edge.The CAS Latency diagram shows general timing for each possible CAS latency setting. Uponcompletionofaburst,assumingnoothercommands havebeeninitiated,theDQswillgoHigh-Z.Afull-pageburst will continue until terminated. (At the end of the page, it will wraptocolumn0andcontinue.) DatafromanyREADburstmaybetruncatedwithasubsequentREADcommand,anddatafromafixed-length READburstmaybeimmediatelyfollowedbydatafroma READcommand.Ineithercase,acontinuousflowofdata canbemaintained.Thefirstdataelementfromthenew burst follows either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. ThenewREADcommandshouldbeissuedx cycles before the clock edge at which the last desired data element is valid, where x equalstheCASlatencyminusone.Thisis showninConsecutiveREADBurstsforCASlatenciesof twoandthree;dataelementn +3iseitherthelastofa burstoffourorthelastdesiredofalongerburst.The512Mb SDRAMusesapipelinedarchitectureandthereforedoes notrequirethe2n rule associated with a prefetch architecture.AREADcommandcanbeinitiatedonanyclockcycle followingapreviousREADcommand.Full-speedrandom read accesses can be performed to the same bank, as showninRandomREADAccesses,oreachsubsequent READmaybeperformedtoadifferentbank. DatafromanyREADburstmaybetruncatedwithasubsequent WRITE command, and data from a fixed-length READburstmaybeimmediatelyfollowedbydatafroma WRITEcommand(subjecttobusturnaroundlimitations). TheWRITEburstmaybeinitiatedontheclockedgeimmediatelyfollowingthelast(orlastdesired)dataelement fromtheREADburst,providedthatI/Ocontentioncanbe avoided. In a given system design, there may be a possibilitythatthedevicedrivingtheinputdatawillgoLow-Z beforetheSDRAMDQsgoHigh-Z.Inthiscase,atleast a single-cycle delay should occur between the last read dataandtheWRITEcommand. 28 READ COMMAND CLK CKE CS RAS CAS WE A0-A9 A11, A12 AUTO PRECHARGE COLUMN ADDRESS HIGH A10 NO PRECHARGE BA0, BA1 BANK ADDRESS TheDQMinputisusedtoavoidI/Ocontention,asshown inFiguresRW1andRW2.TheDQMsignalmustbeasserted (HIGH) at least three clocks prior to theWRITE command(DQMlatencyistwoclocksforoutputbuffers) to suppress data-out from the READ. Once theWRITE commandisregistered,theDQswillgoHigh-Z(orremain High-Z),regardlessofthestateoftheDQMsignal,provided theDQMwasactiveontheclockjustpriortotheWRITE commandthattruncatedtheREADcommand.Ifnot,the secondWRITEwillbeaninvalidWRITE.Forexample,if DQMwasLOWduringT4inFigureRW2,thentheWRITEs atT5andT7wouldbevalid,whiletheWRITEatT6would be invalid. TheDQMsignalmustbede-assertedpriortotheWRITE command(DQMlatencyiszeroclocksforinputbuffers) to ensure that the written data is not masked. Afixed-lengthREADburstmaybefollowedby,ortruncated with, a PRECHARGE command to the same bank (provided thatautoprechargewasnotactivated), and a full-page burst maybetruncatedwithaPRECHARGEcommandtothe samebank.ThePRECHARGEcommandshouldbeissued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minusone.ThisisshownintheREADtoPRECHARGE Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 IS42S86400B, IS42/45S16320B diagramforeachpossibleCASlatency;dataelementn + 3iseitherthelastofaburstoffourorthelastdesiredof alongerburst.FollowingthePRECHARGEcommand,a subsequentcommandtothesamebankcannotbeissued until trpismet.Notethatpartoftherowprechargetimeis hiddenduringtheaccessofthelastdataelement(s). In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burstwithautoprecharge.ThedisadvantageofthePRECHARGEcommandisthatitrequiresthatthecommand and address buses be available at the appropriate time to issuethecommand;theadvantageofthePRECHARGE command is that it can be used to truncate fixed-length or full-page bursts. Full-pageREADburstscanbetruncatedwiththeBURST TERMINATE command, and fixed-length READ bursts maybetruncatedwithaBURSTTERMINATEcommand, providedthatautoprechargewasnotactivated.TheBURST TERMINATEcommandshouldbeissuedx cycles before the clock edge at which the last desired data element is valid, where x equalstheCASlatencyminusone.Thisis shownintheREADBurstTerminationdiagramforeach possibleCASlatency;dataelementn +3isthelastdesired data element of a longer burst. Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 29 IS42S86400B, IS42/45S16320B RW1 - READ to WRITE T0 CLK T1 T2 T3 T4 T5 T6 DQM COMMAND READ NOP NOP NOP NOP NOP WRITE ADDRESS BANK, COL n BANK, COL b tHZ DQ CAS Latency - 2 DON'T CARE DOUT n DOUT n+1 DOUT n+2 DIN b tDS RW2 - READ to WRITE T0 CLK T1 T2 T3 T4 T5 DQM COMMAND READ NOP NOP NOP NOP WRITE ADDRESS BANK, COL n BANK, COL b DQ CAS Latency - 3 tHZ DOUT n DIN b tDS DON'T CARE 30 Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 IS42S86400B, IS42/45S16320B CONSECUTIVE READ BURSTS T0 CLK T1 T2 T3 T4 T5 T6 COMMAND READ NOP NOP NOP READ NOP NOP ADDRESS BANK, COL n BANK, COL b DQ CAS Latency - 2 DOUT n DOUT n+1 DOUT n+2 DOUT n+3 DOUT b DON'T CARE T0 CLK T1 T2 T3 T4 T5 T6 T7 COMMAND READ NOP NOP NOP READ NOP NOP NOP ADDRESS BANK, COL n BANK, COL b DQ CAS Latency - 3 DOUT n DOUT n+1 DOUT n+2 DOUT n+3 DOUT b DON'T CARE Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 31 IS42S86400B, IS42/45S16320B RANDOM READ ACCESSES T0 CLK T1 T2 T3 T4 T5 COMMAND READ READ READ READ NOP NOP ADDRESS BANK, COL n BANK, COL b BANK, COL m BANK, COL x DQ CAS Latency - 2 DOUT n DOUT b DOUT m DOUT x DON'T CARE T0 CLK T1 T2 T3 T4 T5 T6 COMMAND READ READ READ READ NOP NOP NOP ADDRESS BANK, COL n BANK, COL b BANK, COL m BANK, COL x DQ CAS Latency - 3 DOUT n DOUT b DOUT m DOUT x DON'T CARE 32 Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 IS42S86400B, IS42/45S16320B READ BURST TERMINATION T0 CLK T1 T2 T3 T4 T5 T6 COMMAND READ NOP NOP NOP BURST TERMINATE NOP NOP x = 1 cycle ADDRESS BANK a, COL n DQ CAS Latency - 2 DOUT n DOUT n+1 DOUT n+2 DOUT n+3 DON'T CARE T0 CLK T1 T2 T3 T4 T5 T6 T7 COMMAND READ NOP NOP NOP BURST TERMINATE NOP x = 2 cycles NOP NOP ADDRESS BANK, COL n DQ CAS Latency - 3 DOUT n DOUT n+1 DOUT n+2 DOUT n+3 DON'T CARE Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 33 IS42S86400B, IS42/45S16320B ALTERNATING BANK READ ACCESSES T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/ DQML, DQMH tAS tAH A0-A9, A11, A12 A10 BA0, BA1 ROW tAS tAH ROW tAS tAH BANK 0 ACTIVE tCK T1 tCL T2 tCH T3 T4 T5 T6 T7 T8 NOP READ tCMS tCMH NOP ACTIVE NOP READ NOP ACTIVE COLUMN m(2) ENABLE AUTO PRECHARGE ROW ROW COLUMN b(2) ENABLE AUTO PRECHARGE ROW ROW BANK 0 tLZ BANK 3 tOH DOUT m tAC tAC tOH DOUT m+1 tAC BANK 3 tOH DOUT m+2 tAC tRP - BANK 0 tRCD - BANK 3 CAS Latency - BANK 3 tOH DOUT m+3 tAC BANK 0 tOH DOUT b tAC tRCD - BANK 0 DQ tRCD - BANK 0 tRRD tRAS - BANK 0 tRC - BANK 0 CAS Latency - BANK 0 DON'T CARE Notes: 1) CAS latency = 2, Burst Length = 4 2) x16: A11 and A12 = "Don't Care" x8: A12 = "Don't Care" 34 Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 IS42S86400B, IS42/45S16320B READ - FULL-PAGE BURST T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/ DQML, DQMH tAS tAH A0-A9, A11, A12 A10 BA0, BA1 DQ ROW tAS tAH ROW tAS tAH BANK ACTIVE tCK T1 tCL T2 tCH T3 T4 T5 T6 Tn+1 Tn+2 Tn+3 Tn+4 NOP READ NOP NOP NOP NOP NOP BURST TERM NOP NOP tCMS tCMH COLUMN m(2) BANK tAC tLZ tRCD CAS Latency DOUT m tAC tAC DOUT m+1 tAC DOUT m+2 tAC DOUT m-1 tAC DOUT m tHZ DOUT m+1 tOH DON'T CARE UNDEFINED tOH tOH tOH tOH tOH each row (x16) has 512 locations(3) Full page Full-page burst not self-terminating. completion Use BURST TERMINATE command. Notes: 1) CAS latency = 2, Burst Length = Full Page 2) x16: A11 and A12 = "Don't Care" x8: A12 = "Don't Care" 3) x16: Each row has 1,024 locations. x8: Each row has 2,048 locations. Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 35 IS42S86400B, IS42/45S16320B READ - DQM OPERATION T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/ DQML, DQMH tAS tAH A0-A9, A11, A12 A10 BA0, BA1 DQ ROW tAS tAH ROW tAS tAH BANK ACTIVE tCK T1 tCL T2 tCH T3 T4 T5 T6 T7 T8 NOP READ tCMS tCMH NOP NOP NOP NOP NOP NOP COLUMN m(2) ENABLE AUTO PRECHARGE DISABLE AUTO PRECHARGE BANK tAC tLZ tRCD CAS Latency tOH DOUT m tHZ tLZ tAC tOH DOUT m+2 tAC tOH DOUT m+3 tHZ DON'T CARE UNDEFINED Notes: 1) CAS latency = 2, Burst Length = 4 2) x16: A11 and A12 = "Don't Care" x8: A12 = "Don't Care" 36 Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 IS42S86400B, IS42/45S16320B READ to PRECHARGE T0 CLK T1 T2 T3 T4 T5 tRP T6 T7 COMMAND READ NOP NOP NOP PRECHARGE NOP ACTIVE NOP ADDRESS BANK a, COL n BANK (a or all) BANK a, ROW tRQL DQ CAS Latency - 2 DOUT n DOUT n+1 DOUT n+2 DOUT n+3 High-Z DON'T CARE T0 CLK T1 T2 T3 T4 T5 tRP T6 T7 COMMAND READ NOP NOP NOP PRECHARGE NOP NOP ACTIVE ADDRESS BANK, COL n BANK, COL b BANK a, ROW tRQL DQ CAS Latency - 3 DOUT n DOUT n+1 DOUT n+2 DOUT n+3 High-Z DON'T CARE Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 37 IS42S86400B, IS42/45S16320B WRITES WRITEburstsareinitiatedwithaWRITEcommand,as showninWRITECommanddiagram. AnexampleisshowninWRITEtoWRITEdiagram.Data n + 1 is either the last of a burst of two or the last desired ofalongerburst.The512MbSDRAMusesapipelined architectureandthereforedoesnotrequirethe2n rule associatedwithaprefetcharchitecture.AWRITEcommand can be initiated on any clock cycle following a previous WRITEcommand.Full-speedrandomwriteaccesseswithin a page can be performed to the same bank, as shown in RandomWRITECycles,oreachsubsequentWRITEmay be performed to a different bank. DataforanyWRITEburstmaybetruncatedwithasubsequentREADcommand,anddataforafixed-lengthWRITE burstmaybeimmediatelyfollowedbyasubsequentREAD command.OncetheREADcommandisregistered,the datainputswillbeignored,andWRITEswillnotbeexecuted.AnexampleisshowninWRITEtoREAD.Datan + 1 is either the last of a burst of two or the last desired of a longer burst. Data for a fixed-length WRITE burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that auto precharge was not activated), and a full-pageWRITE burst may be truncated with a PRECHARGE command to the same bank.The PRECHARGEcommandshouldbeissuedtdpl after the clock edge at which the last desired input data element isregistered.Theautoprechargemoderequiresatdpl of atleastoneclockplustime,regardlessoffrequency.In addition,whentruncatingaWRITEburst,theDQMsignal must be used to mask input data for the clock edge prior to,andtheclockedgecoincidentwith,thePRECHARGE command.AnexampleisshownintheWRITEtoPRECHARGEdiagram.Datan+1 is either the last of a burst oftwoorthelastdesiredofalongerburst.Followingthe PRECHARGEcommand,asubsequentcommandtothe same bank cannot be issued until trp is met. In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (asdescribedabove) provides the same operation that would result from the same fixed-length burst with auto precharge.ThedisadvantageofthePRECHARGE command isthatitrequiresthatthecommandandaddressbusesbe availableattheappropriatetimetoissuethecommand;the advantageofthePRECHARGEcommandisthatitcanbe used to truncate fixed-length or full-page bursts. Fixed-lengthorfull-pageWRITEburstscanbetruncated withtheBURSTTERMINATEcommand.WhentruncatingaWRITEburst,theinputdataappliedcoincidentwith theBURSTTERMINATEcommandwillbeignored.The lastdatawritten(providedthatDQMisLOWatthattime) will be the input data applied one clock previous to the BURSTTERMINATEcommand.ThisisshowninWRITE BurstTermination,wheredatan is the last desired data element of a longer burst. Integrated Silicon Solution, Inc. -- www.issi.com WRITE COMMAND CLK CKE CS RAS CAS WE A0-A9 A11, A12 AUTO PRECHARGE COLUMN ADDRESS HIGH A10 NO PRECHARGE BA0, BA1 BANK ADDRESS Thestartingcolumnandbankaddressesareprovidedwith theWRITEcommand,andautoprechargeiseitherenabled or disabled for that access. If auto precharge is enabled, the row being accessed is precharged at the completion of theburst.ForthegenericWRITEcommandsusedinthe following illustrations, auto precharge is disabled. DuringWRITEbursts,thefirstvaliddata-in element will be registered coincident with the WRITEcommand.Subsequent data elements will be registered on each successive positiveclockedge.Uponcompletionofafixed-lengthburst, assuming no other commands have been initiated, the DQswillremainHigh-Zandanyadditionalinputdatawill beignored(seeWRITEBurst).Afull-pageburstwillcontinue until terminated. (At the end of the page, it will wrap tocolumn0andcontinue.) DataforanyWRITEburstmaybetruncatedwithasubsequentWRITEcommand,anddataforafixed-lengthWRITE burst may be immediately followed by data for a WRITE command. The new WRITE command can be issued on anyclockfollowingthepreviousWRITEcommand,andthe data provided coincident with the new command applies to the new command. 38 Rev. C 08/27/09 IS42S86400B, IS42/45S16320B WRITE BURST T0 CLK T1 T2 T3 COMMAND WRITE NOP NOP NOP ADDRESS BANK, COL n DQ DIN n DIN n+1 DON'T CARE WRITE TO WRITE T0 CLK T1 T2 COMMAND WRITE NOP WRITE ADDRESS BANK, COL n BANK, COL b DQ DIN n DIN n+1 DIN b DON'T CARE RANDOM WRITE CYCLES T0 CLK T1 T2 T3 COMMAND WRITE WRITE WRITE WRITE ADDRESS BANK, COL n BANK, COL b BANK, COL m BANK, COL x DQ DIN n DIN b DIN m DIN x Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 39 IS42S86400B, IS42/45S16320B WRITE to READ T0 CLK T1 T2 T3 T4 T5 COMMAND WRITE NOP READ NOP NOP NOP ADDRESS BANK, COL n BANK, COL b DQ DIN n DIN n+1 CAS Latency - 2 DOUT b DOUT b+1 DON'T CARE WP1 - WRITE to PRECHARGE T0 CLK T1 T2 T3 T4 T5 T6 DQM tRP COMMAND WRITE NOP NOP PRECHARGE NOP ACTIVE NOP ADDRESS BANK a, COL n BANK (a or all) BANK a, ROW tDPL DQ DIN n DIN n+1 DIN n+2 DON'T CARE 40 Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 IS42S86400B, IS42/45S16320B WP2 - WRITE to PRECHARGE T0 CLK T1 T2 T3 T4 T5 T6 DQM tRP COMMAND WRITE NOP NOP PRECHARGE NOP NOP ACTIVE ADDRESS BANK a, COL n BANK (a or all) BANK a, ROW tDPL DQ DIN n DIN n+1 DON'T CARE WRITE Burst Termination T0 CLK T1 T2 COMMAND WRITE BURST TERMINATE NEXT COMMAND ADDRESS BANK, COL n (ADDRESS) DQ DIN n (DATA) DON'T CARE Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 41 IS42S86400B, IS42/45S16320B WRITE - FULL PAGE BURST T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/DQML DQMH tAS tAH A0-A9, A11, A12 A10 BA0, BA1 DQ tRCD ROW tAS tAH ROW tAS tAH BANK BANK tDS tDH DIN m tDS tDH DIN m+1 tDS tDH DIN m+2 tDS tDH tDS tDH tDS tDH DIN m+3 DIN m-1 DON'T CARE COLUMN m(2) ACTIVE NOP WRITE NOP NOP NOP NOP BURST TERM NOP T1 tCK tCL T2 tCH T3 T4 T5 Tn+1 Tn+2 tCMS tCMH Full page completed Notes: 1) Burst Length = Full Page 2) x16: A11 and A12 = "Don't Care" x8: A12 = "Don't Care" 42 Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 IS42S86400B, IS42/45S16320B WRITE - DQM OPERATION T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/DQML DQMH tAS tAH A0-A9, A11, A12 A10 BA0, BA1 DQ ROW tAS tAH ROW tAS tAH BANK ACTIVE tCK T1 tCL T2 tCH T3 T4 T5 T6 T7 NOP WRITE tCMS tCMH NOP NOP NOP NOP NOP COLUMN m(2) ENABLE AUTO PRECHARGE DISABLE AUTO PRECHARGE BANK tDS tDH tDS tDH DIN m+2 tDS tDH DIN m tRCD DIN m+3 DON'T CARE Notes: 1) Burst Length = 4 2) x16: A11 and A12 = "Don't Care" x8: A12 = "Don't Care" Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 43 IS42S86400B, IS42/45S16320B ALTERNATING BANK WRITE ACCESSES T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/DQML DQMH tAS tAH A0-A9, A11, A12 A10 BA0, BA1 ROW tAS tAH ROW tAS tAH BANK 0 BANK 0 tDS DQ tRCD - BANK 0 tRRD tRAS - BANK 0 tRC - BANK 0 tDH tDS tDH DIN m+1 COLUMN m(2) ENABLE AUTO PRECHARGE ROW BANK 1 tDS tDH DIN m+2 tDS tDH BANK 1 tDS tDH DIN b tDS tDH tDS tDH ROW COLUMN b(2) ENABLE AUTO PRECHARGE ROW BANK 0 tDS tDH ROW ACTIVE NOP WRITE tCMS tCMH NOP ACTIVE NOP WRITE NOP NOP ACTIVE T1 T2 T3 T4 T5 T6 T7 T8 T9 tCK tCL tCH DIN m DIN m+3 DIN b+1 DIN b+2 DIN b+3 tRCD - BANK 0 tDPL - BANK 1 tDPL - BANK 0 tRCD - BANK 1 tRP - BANK 0 DON'T CARE Notes: 1) Burst Length = 4 2) x16: A11 and A12 = "Don't Care" x8: A12 = "Don't Care" 44 Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 IS42S86400B, IS42/45S16320B CLOCK SUSPEND Clock suspend mode occurs when a column access/burst isinprogressandCKEisregisteredLOW.Intheclock suspendmode,theinternalclockisdeactivated,"freezing" the synchronous logic. ForeachpositiveclockedgeonwhichCKEissampled LOW,thenextinternalpositiveclockedgeissuspended. Any command or data present on the input pins at the time ofasuspendedinternalclockedgeisignored;anydata presentontheDQpinsremainsdriven;andburstcounters are not incremented, as long as the clock is suspended. (Seefollowingexamples.) ClocksuspendmodeisexitedbyregisteringCKEHIGH; the internal clock and related operation will resume on the subsequentpositiveclockedge. Clock Suspend During WRITE Burst T0 CLK T1 T2 T3 T4 T5 CKE INTERNAL CLOCK COMMAND NOP WRITE NOP NOP ADDRESS BANK a, COL n DQ DIN n DIN n+1 DIN n+2 DON'T CARE Clock Suspend During READ Burst T0 CLK T1 T2 T3 T4 T5 T6 CKE INTERNAL CLOCK COMMAND READ NOP NOP NOP NOP NOP ADDRESS BANK a, COL n DQ DOUT n DOUT n+1 DOUT n+2 DOUT n+3 DON'T CARE Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 45 IS42S86400B, IS42/45S16320B CLOCK SUSPEND MODE T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/DQML DQMH tAS tAH A0-A9, A11, A12 A10 tAS tAH BA0, BA1 BANK tAC DQ tLZ DOUT m tOH DON'T CARE UNDEFINED tAC tHZ DOUT m+1 BANK tDS tDH DIN e DIN e+1 COLUMN m(2) tAS tAH COLUMN n(2) READ NOP tCMS tCMH NOP NOP NOP NOP WRITE NOP tCK T1 tCL T2 tCH T3 T4 T5 T6 T7 T8 T9 tCKS tCKH Notes: 1) CAS latency = 3, Burst Length = 2, Auto Precharge is disabled. 2) x16: A11 and A12 = "Don't Care" x8: A12 = "Don't Care" 46 Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 IS42S86400B, IS42/45S16320B PRECHARGE ThePRECHARGEcommand(seefigure)isusedtodeactivate the open row in a particular bank or the open row in allbanks.Thebank(s)willbeavailableforasubsequentrow access some specified time (trp)afterthePRECHARGE command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only onebankistobeprecharged,inputsBA0,BA1selectthe bank.Whenallbanksaretobeprecharged,inputsBA0, BA1aretreatedas"Don'tCare."Onceabankhasbeen precharged, it is in the idle state and must be activated priortoanyREADorWRITEcommandsbeingissuedto that bank. PRECHARGE Command CLK CKE CS RAS CAS WE A0-A9, A11, A12 ALL BANKS HIGH POWER-DOWN Power-downoccursifCKEisregisteredLOWcoincident withaNOPorCOMMANDINHIBITwhennoaccesses are in progress. If power-down occurs when all banks are idle,thismodeisreferredtoasprechargepower-down; if power-down occurs when there is a row active in either bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers,excludingCKE,formaximumpowersavingswhile instandby.Thedevicemaynotremaininthepower-down statelongerthantherefreshperiod(64ms)sincenorefresh operations are performed in this mode. Thepower-downstateisexitedbyregisteringaNOPor COMMANDINHIBITandCKEHIGHatthedesiredclock edge (meeting tcks).Seefigure"Power-Down". A10 BANK SELECT BA0, BA1 BANK ADDRESS POWER-DOWN CLK tCKS CKE tCKS COMMAND NOP Input buffers gated off NOP ACTIVE tRCD tRAS tRC DON'T CARE All banks idle Enter power-down mode Exit power-down mode less than 64ms Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 47 IS42S86400B, IS42/45S16320B POWER-DOWN MODE CYCLE T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/DQML DQMH A0-A9, A11, A12 ALL BANKS A10 SINGLE BANK tAS tAH BA0, BA1 BANK PRECHARGE tCK T1 tCL T2 tCH tCKS Tn+1 tCKS Tn+2 NOP NOP NOP ACTIVE ROW ROW BANK DQ High-Z Two clock cycles Precharge all active banks All banks idle, enter power-down mode Input buffers gated off while in power-down mode All banks idle Exit power-down mode DON'T CARE 48 Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 IS42S86400B, IS42/45S16320B BURST READ/SINGLE WRITE Theburstread/singlewritemodeisenteredbyprogramming the write burst mode bit (M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the access ofasinglecolumnlocation(burstofone),regardlessof theprogrammedburstlength.READcommandsaccess columns according to the programmed burst length and sequence,justasinthenormalmodeofoperation(M9 =0). SDRAMssupportCONCURRENTAUTOPRECHARGE. FourcaseswhereCONCURRENTAUTOPRECHARGE occurs are defined below. READ with Auto Precharge 1.InterruptedbyaREAD(withorwithoutautoprecharge): AREADtobankmwillinterruptaREADonbankn, CAS latency later.The PRECHARGE to bank n will beginwhentheREADtobankmisregistered. 2.InterruptedbyaWRITE(withorwithoutautoprecharge): AWRITEtobankmwillinterruptaREADonbankn whenregistered.DQMshouldbeusedthreeclocksprior totheWRITEcommandtopreventbuscontention.The PRECHARGEtobanknwillbeginwhentheWRITEto bank m is registered. CONCURRENT AUTO PRECHARGE Anaccesscommand(READorWRITE)toanotherbank while an access command with auto precharge enabled is executingisnotallowedbySDRAMs,unlesstheSDRAM supports CONCURRENT AUTO PRECHARGE. ISSI READ With Auto Precharge interrupted by a READ T0 CLK COMMAND BANK n NOP READ - AP BANK n T1 T2 T3 T4 T5 T6 T7 NOP READ - AP BANK m NOP NOP NOP NOP Page Active READ with Burst of 4 Interrupt Burst, Precharge tRP - BANK n Idle tRP - BANK m Precharge Internal States BANK m ADDRESS DQ CAS Latency - 3 (BANK n) Page Active BANK n, COL a BANK n, COL b READ with Burst of 4 DOUT a DOUT a+1 DOUT b DOUT b+1 DON'T CARE CAS Latency - 3 (BANK m) READ With Auto Precharge interrupted by a WRITE T0 CLK COMMAND BANK n READ - AP BANK n T1 T2 T3 T4 T5 T6 T7 NOP NOP NOP WRITE - AP BANK m NOP NOP NOP Idle tDPL - BANK m Write-Back READ with Burst of 4 Page Active Page Active BANK n, COL a BANK m, COL b Interrupt Burst, Precharge tRP - BANK n WRITE with Burst of 4 Internal States BANK m ADDRESS DQM DQ DOUT a CAS Latency - 3 (BANK n) DIN b DIN b+1 DIN b+2 DIN b+3 DON'T CARE Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 49 IS42S86400B, IS42/45S16320B WRITE with Auto Precharge 3.InterruptedbyaREAD(withorwithoutautoprecharge): AREADtobankmwillinterruptaWRITEonbanknwhen registered, with the data-out appearing (CAS latency) later.ThePRECHARGEtobanknwillbeginaftertdpl is met, where tdplbeginswhentheREADtobankmis registered.ThelastvalidWRITE to bank n will be data-in registeredoneclockpriortotheREADtobankm. 4.InterruptedbyaWRITE(withorwithoutautoprecharge): AWRITE to bank m will interrupt a WRITE on bank n when registered.ThePRECHARGEtobanknwillbeginafter tdpl is met, where tdplbeginswhentheWRITEtobank misregistered.ThelastvaliddataWRITEtobankn willbedataregisteredoneclockpriortoaWRITEto bank m. WRITE With Auto Precharge interrupted by a READ T0 CLK T1 T2 T3 T4 T5 T6 T7 COMMAND NOP WRITE - AP BANK n NOP READ - AP BANK m NOP NOP NOP NOP BANK n Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back tDPL - BANK n Precharge tRP - BANK n tRP - BANK m Precharge Internal States BANK m Page Active BANK n, COL a BANK m, COL b READ with Burst of 4 ADDRESS DQ DIN a DIN a+1 CAS Latency - 3 (BANK m) DOUT b DOUT b+1 DON'T CARE WRITE With Auto Precharge interrupted by a WRITE T0 CLK T1 T2 T3 T4 T5 T6 T7 COMMAND NOP WRITE - AP BANK n NOP NOP WRITE - AP BANK m NOP NOP NOP BANK n Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back tDPL - BANK n Precharge tRP - BANK n tDPL - BANK m Write-Back Internal States BANK m Page Active BANK n, COL a BANK m, COL b WRITE with Burst of 4 ADDRESS DQ DIN a DIN a+1 DIN a+2 DIN b DIN b+1 DIN b+2 DIN b+3 DON'T CARE 50 Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 IS42S86400B, IS42/45S16320B SINGLE READ WITH AUTO PRECHARGE T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/DQML DQMH tAS A0-A9, A11, A12 A10 BA0, BA1 DQ tAH ROW tAS tAH ROW tAS tAH BANK ACTIVE tCK T1 tCL T2 tCH T3 T4 T5 T6 T7 T8 NOP NOP NOP READ NOP NOP ACTIVE NOP tCMS tCMH COLUMN m(2) ENABLE AUTO PRECHARGE ROW ROW BANK tAC tOH DOUT m tRCD tRAS tRC CAS Latency tRP tHZ BANK DON'T CARE UNDEFINED Notes: 1) CAS latency = 2, Burst Length = 1 2) x16: A11 and A12 = "Don't Care" x8: A12 = "Don't Care" Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 51 IS42S86400B, IS42/45S16320B SINGLE READ WITHOUT AUTO PRECHARGE T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/DQML DQMH tAS tAH A0-A9, A11, A12 A10 BA0, BA1 DQ ROW tAS tAH ROW tAS tAH BANK ACTIVE tCK T1 tCL T2 tCH T3 T4 T5 T6 T7 T8 NOP READ tCMS tCMH NOP NOP PRECHARGE NOP ACTIVE NOP COLUMN m(2) ALL BANKS ROW ROW DISABLE AUTO PRECHARGE BANK tAC tLZ CAS Latency tOH DOUT m tRCD tRAS tRC tHZ SINGLE BANK BANK BANK DON'T CARE tRP UNDEFINED Notes: 1) CAS latency = 2, Burst Length = 1 2) x16: A11 and A12 = "Don't Care" x8: A12 = "Don't Care" 52 Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 IS42S86400B, IS42/45S16320B READ WITH AUTO PRECHARGE T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/DQML DQMH tAS tAH A0-A9, A11, A12 A10 BA0, BA1 DQ ROW tAS tAH ROW tAS tAH BANK ACTIVE tCK T1 tCL T2 tCH T3 T4 T5 T6 T7 T8 NOP READ tCMS tCMH NOP NOP NOP NOP NOP ACTIVE COLUMN m(2) ENABLE AUTO PRECHARGE ROW ROW BANK tAC tLZ CAS Latency tAC DOUT m tOH tAC DOUT m+1 tOH tAC DOUT m+2 tOH tRP tHZ DOUT m+3 tOH BANK tRCD tRAS tRC DON'T CARE UNDEFINED Notes: 1) CAS latency = 2, Burst Length = 4 2) x16: A11 and A12 = "Don't Care" x8: A12 = "Don't Care" Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 53 IS42S86400B, IS42/45S16320B READ WITHOUT AUTO PRECHARGE T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/DQML DQMH tAS tAH A0-A9, A11, A12 A10 BA0, BA1 DQ ROW tAS tAH ROW tAS tAH BANK ACTIVE tCK T1 tCL T2 tCH T3 T4 T5 T6 T7 T8 NOP READ tCMS tCMH NOP NOP NOP PRECHARGE NOP ACTIVE COLUMN m(2) ALL BANKS ROW ROW DISABLE AUTO PRECHARGE BANK tAC tLZ CAS Latency tAC DOUT m tOH tAC DOUT m+1 tOH SINGLE BANK BANK tAC DOUT m+2 tOH tRP tHZ DOUT m+3 tOH DON'T CARE UNDEFINED BANK tRCD tRAS tRC Notes: 1) CAS latency = 2, Burst Length = 4 2) x16: A11 and A12 = "Don't Care" x8: A12 = "Don't Care" 54 Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 IS42S86400B, IS42/45S16320B SINGLE WRITE WITH AUTO PRECHARGE T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/DQML, DQMH A0-A9, A11, A12 A10 BA0, BA1 tAS tAH ACTIVE tCK T1 tCL T2 tCH T3 T4 T5 T6 T7 T8 T9 NOP NOP NOP WRITE tCMS tCMH NOP NOP NOP ACTIVE NOP ROW tAS tAH ROW tAS tAH BANK COLUMN m(2) ENABLE AUTO PRECHARGE ROW ROW BANK tDS tDH BANK DQ tRCD tRAS tRC DIN m tDPL tRP DON'T CARE Notes: 1) Burst Length = 1 2) x16: A11 and A12 = "Don't Care" x8: A12 = "Don't Care" Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 55 IS42S86400B, IS42/45S16320B SINGLE WRITE - WITHOUT AUTO PRECHARGE T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/DQML DQMH tAS tAH A0-A9, A11, A12 A10 BA0, BA1 ROW tAS tAH ROW tAS tAH BANK BANK tDS tDH DQ tRCD tRAS tRC DIN m tDPL(3) tRP DON'T CARE COLUMN m(2) DISABLE AUTO PRECHARGE tCK T1 tCL T2 tCH T3 T4 T5 T6 T7 T8 ACTIVE NOP WRITE tCMS tCMH NOP NOP PRECHARGE NOP ACTIVE NOP ROW ALL BANKS ROW SINGLE BANK BANK BANK Notes: 1) Burst Length = 1 2) x16: A11 and A12 = "Don't Care" x8: A12 = "Don't Care" 3) tras must not be violated. 56 Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 IS42S86400B, IS42/45S16320B WRITE - WITH AUTO PRECHARGE T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/DQML DQMH tAS tAH A0-A9, A11, A12 A10 BA0, BA1 ROW tAS tAH ROW tAS tAH BANK ACTIVE tCK T1 tCL T2 tCH T3 T4 T5 T6 T7 T8 T9 NOP WRITE tCMS tCMH NOP NOP NOP NOP NOP NOP ACTIVE COLUMN m(2) ENABLE AUTO PRECHARGE ROW ROW BANK tDS tDH tDS tDH DIN m+1 tDS tDH DIN m+2 tDS tDH BANK DQ tRCD tRAS tRC DIN m DIN m+3 tDPL tRP DON'T CARE Notes: 1) Burst Length = 4 2) x16: A11 and A12 = "Don't Care" x8: A12 = "Don't Care" Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 57 IS42S86400B, IS42/45S16320B WRITE - WITHOUT AUTO PRECHARGE T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/DQML DQMH tAS tAH A0-A9, A11, A12 A10 BA0, BA1 ROW tAS tAH ROW tAS tAH BANK ACTIVE tCK T1 tCL T2 tCH T3 T4 T5 T6 T7 T8 NOP WRITE tCMS tCMH NOP NOP NOP PRECHARGE NOP ACTIVE COLUMN m(2) ALL BANKS ROW ROW DISABLE AUTO PRECHARGE BANK tDS tDH tDS tDH DIN m+1 tDS tDH DIN m+2 tDS tDH SINGLE BANK BANK BANK DQ tRCD tRAS tRC DIN m DIN m+3 tDPL(3) tRP DON'T CARE Notes: 1) Burst Length = 4 2) x16: A11 and A12 = "Don't Care" x8: A12 = "Don't Care" 3) tras must not be violated. 58 Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 IS42S86400B, IS42/45S16320B ORDERING INFORMATION - VDD = 3.3V Commercial Range: 0oC to +70oC Frequency 166MHz 143MHz 133MHz Speed (ns) 6 7 7.5 Order Part No. IS42S86400B-6TL IS42S16320B-6TL IS42S16320B-6BL IS42S86400B-7TL IS42S16320B-7TL IS42S16320B-7BL IS42S86400B-75ETL IS42S16320B-75ETL Package 54-PinTSOPII,Lead-free 54-PinTSOPII,Lead-free 54-ballBGA,Lead-free 54-PinTSOPII,Lead-free 54-PinTSOPII,Lead-free 54-ballBGA,Lead-free 54-PinTSOPII,Lead-free 54-PinTSOPII,Lead-free Industrial Range: -40oC to +85oC Frequency Speed (ns) Order Part No. Package 166MHz 6 IS42S86400B-6TLI 54-PinTSOPII,Lead-free IS42S16320B-6TLI 54-PinTSOPII,Lead-free IS42S16320B-6BLI 54-ballBGA,Lead-free 143MHz 7 IS42S86400B-7TLI 54-PinTSOPII,Lead-free IS42S16320B-7TLI 54-PinTSOPII,Lead-free IS42S16320B-7BLI 54-ballBGA,Lead-free 133MHz 7.5 IS42S86400B-75ETLI 54-PinTSOPII,Lead-free IS42S16320B-75ETLI 54-PinTSOPII,Lead-free P leasecontactISSISalesforleadedpartsupportandstatusofBGApackageoption. Automotive Range: -40oC to +85oC Frequency Speed (ns) Order Part No. Package 143MHz 7 IS45S16320B-7TLA1 54-PinTSOPII,Lead-free IS45S16320B-7BLA1 54-ballBGA,Lead-free P leasecontactISSISalesforleadedpartsupportandstatusofBGApackageoption. Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 59 IS42S86400B, IS42/45S16320B 60 Integrated Silicon Solution, Inc. -- www.issi.com Rev. C 08/27/09 TOP VIEW PIN A1 INDEX E1 w e BOTTOM VIEW PIN A1 CORNER 1 98 7 3 21 2 3 78 9 Symbol A B C D E F D1 D Dimension in mm Min A B C D E b Nom Max A 1.20 A1 e 0.25 0.40 b F G 6.50 0.40 0.45 0.50 t 0.20 G H J 3.20 0.1 W H J 2.05 D 12.9 13.0 13.1 D1 6.40 E 10.9 11.0 11.1 E1 B E 0.1 A 6.40 e A 3.20 0.1 5.50 0.80 IS42S86400B, IS42/45S16320B 0.10 C A1 A 90X 0.10 C C 54L 11x13mm W-BGA Package Outline 10/16/2007 Integrated Silicon Solution, Inc. -- www.issi.com t Rev. C 08/27/09 61 |
Price & Availability of IS42S16320B-7BL |
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